1. Field of the Invention
This invention relates to an electronic circuit and more particularly to an internal clock signal generation circuit having external clock detection and a selectable internal clock pulse.
2. Description of the Relevant Art
Circuits used for generating a plurality of clocking pulses are often referred to as clocking circuits. Clocking circuits are beneficial in setting the operating speed of a system, or one or more devices within the system. Clocking pulses output from the clocking circuit must oftentimes undergo shaping or some form of filtration to ensure a stream of pulses more readily received by a load device.
A popular form of wave shaping or filtration involves use of a phase-locked loop (PLL). PLLs operate by detecting an input stream of pulses and locking upon the input pulses (in phase and frequency) using a low pass filter and voltage controlled oscillator connected in a feedback configuration. The input pulses are thereby operated upon by the PLL to present an output stream of pulses with similar phase and frequency as the input pulses but at a more consistent frequency and duty cycle for the duration of the input pulses. Thus, PLLs are used to filter out short term fluctuations in the input stream of pulses in order to present a stream of output pulses more suitable to an output-connected load device. As defined hereinbelow, input pulses are referred to as those pulses within an external clock signal, and output pulses are those pulses within an internal clock signal. It is therefore appreciated that the internal clock signal is oftentimes dissimilar from the external clock signal. The internal clock signal is generally tuned to match the operating characteristics of the load device.
A problem often encountered with PLLs is their inherent delay in locking onto the external clock signal. PLLs require passage of numerous external clock pulse cycles before an internal clock signal is generated having a frequency and phase similar to the external clock signal. While PLLs achieve good wave shaping and consistent filtration of external clock signal fluctuation, PLLs are inadequate if instantaneous or near instantaneous internal clock signal generation is required. In many instances, manufacturer specification requires the internal clock signal to track the external clock signal between static and dynamic frequency. Tracking must occur "on the fly" with minimal delay between application of external clock signal and generation of internal clock signal. Wave shaping and frequency/phase fluctuation filtration techniques of PLLs is therefore needed without PLL start-up delay.
One way in which to achieve wave shaping with nearly instantaneous internal clock signal generation is to use a monostable multivibrator coupled between the external clock signal and the internal clock signal. The monostable multivibrator (often referred to as a "one-shot") triggers from the leading or falling edge of each pulse within the external clock signal and provides a set duration pulse thereafter. An illustration of one-shot 10 placed between external clock signal and internal clock signal is illustrated in FIG. 1. Provided the external clock signal maintains a constant frequency, the one-shot circuit assures that duty cycle of the internal clock signal will also remain constant.
One-shot 10 is preferred over a PLL not only for its on-the-fly tracking of the external clock during start-up, but also for its tunability to the internal timing specification of the load device 12. Specifically, one-shot 10 is designed to change to a quasi-stable state for a fixed period of time, and the fixed period of time is set to exceed the worst-case speed path within load device 12. By setting the quasi-stable state of one-shot 10 to a duration greater than the worst-case speed path, load device 12 is assured of operability. However, the quasi-stable state must not be too high, as would cause the stable state duration to be less than the worst-case speed path. As defined herein, worst-case speed path refers to a time duration necessary to propagate a signal through the path, wherein the path is one having the greatest delay through micro components arranged between two clocked elements within the load device.
FIG. 2 helps illustrate the advantages as well as the disadvantages of using a one-shot for generating an internal clock signal. As shown, a one-shot triggers from one edge (a leading edge as shown in the example of FIG. 2) of external clock signal at time T1. Regardless of the duration of the external clock signal pulse, the quasistable state will continue from T1 to a fixed duration time T2 thereafter. The process is repeated at each leading edge of pulses within external clock signal to present an internal clock signal of fixed high (or low) pulse duration. As defined herein, high pulse refers to a voltage magnitude which is greater than the magnitude of a low pulse. The magnitude of the low pulse is therefore closer to ground potential than the magnitude of the high pulse.
The duration of the quasi-stable state of one-shot 10 is shown in FIG. 2 as reference numeral 14. Regardless of the external clock signal operating frequency (either frequency F1 or frequency F2), quasi-stable state 14 remains constant. Preferably, quasi-stable state duration 14 is fixed at or near a 50% duty cycle for higher frequency operation F2. By defining quasi-stable state duration to exceed worst-case speed path in a 50% or near 50% duty cycle, a maximum external clock signal can be defined (e.g., maximum frequency F2) to drive load device 12. A problem often presents itself, however, whenever wafer fabrication process variability occurs. If a wafer is fabricated embodying load device 12 which cannot operate at a specified speed value, then it may be incapable of operating at the chosen quasi-stable state duration 14. The die tested upon a wafer which fails maximum speed requirements set by one-shot quasi-stable state must therefore be discarded. Even if the operator slows the frequency of the external clock signal, the internal clock signal quasi-stable state duration 14 nonetheless remains constant--at a time duration less than the operable speed of the die. The die would only operate correctly if the one shot quasi-stable state duration is increased.
Accordingly, the defective die are determined solely from the operating characteristics of one-shot 10, regardless of user-defined application. There may be instances in which the user does not require a fast external clock signal and would be quite content with lowering the external clocking frequency if the price of the load device is lessened. It would therefore be advantageous to provide means for salvaging die having load devices which may not operate at maximum frequency, but which operate at some frequency below maximum. For those load devices which operate at lower frequencies, it would be desirable to lessen the external clock signal frequency and provide a longer duration quasi-stable state. The newly defined internal clock signal quasi-stable state duration would correspondingly be greater than the worst-case speed path of the slower operating die (load device).